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STK14C88-3 256 kbit (32k x 8) autostore nvsram cypress semiconductor corporation ? 198 champion court ? san jose , ca 95134-1709 ? 408-943-2600 document number: 001-50592 rev. *d revised february 11, 2011 features 35 ns and 45 ns access times automatic nonvolatile store on power loss nonvolatile store under hardware or software control automatic recall to sram on power up unlimited read/write endurance unlimited recall cycles 1,000,000 store cycles 100 year data retention single 3.3v + 0.3v power supply commercial and industrial temperatures 32-pin (300mil) soic and 32-pin (600 mil) pdip packages rohs compliance functional description the cypress STK14C88-3 is a 256 kb fast static ram with a nonvolatile element in each memory cell. the embedded nonvolatile elements incorporate quantumtrap technology producing the world?s most reliable nonvolatile memory. the sram provides unlimited read and write cycles, while independent, nonvolatile data resides in the highly reliable quantumtrap cell. data transfers from the sram to the nonvolatile elements (the store operation) takes place automatically at power down. on power up, data is restored to the sram (the recall operation) from the nonvolatile memory. both the store and recall operations are also available under software control. store/ recall control power control software detect static ram array 512 x 512 quantum trap 512 x 512 store recall column i/o column dec row decoder input buffers oe ce we hsb v cc v cap a 13 - a 0 a 0 a 1 a 2 a 3 a 4 a 10 a 5 a 6 a 7 a 8 a 9 a 11 a 12 a 13 a 14 dq 0 dq 1 dq 2 dq 3 dq 4 dq 5 dq 6 dq 7 logic block diagram [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 2 of 18 contents features................................................................................ 1 functional description........................................................ 1 logic block diagram........................................................... 1 contents ............................................................................... 2 pin configurations .............................................................. 3 device operation ................................................................. 4 sram read .......................................................................... 4 sram write .......................................................................... 4 autostore operation ........................................................... 4 autostore inhibit mode ....................................................... 4 hardware store (hsb) operation.................................... 5 hardware recall (power up)........................................... 5 software store .................................................................. 5 software recall................................................................ 6 preventing store............................................................... 6 hardware protect................................................................. 6 noise considerations.......................................................... 6 low average active power................................................. 6 best practices...................................................................... 7 maximum ratings................................................................ 8 dc electrical characteristics ............................................. 8 data retention and endurance .... ...................................... 9 capacitance ......................................................................... 9 thermal resistance............................................................. 9 ac test conditions ............................................................. 9 ac switching characteristics ........................................... 10 sram read cycle ....................................................... 10 switching waveforms ....................................................... 10 switching waveforms ....................................................... 11 autostore or power up recall ..................................... 12 switching waveforms ....................................................... 12 software controlled store/recall cycle................... 13 switching waveforms ....................................................... 13 hardware store cycle .................................................... 14 switching waveforms ........................................................ 14 part numbering nomenclature.......................................... 15 ordering information......................................................... 15 package diagrams............................................................. 16 document history page ..................................................... 17 sales, solutions and legal information .......................... 17 worldwide sales and design supp ort............. ............. 17 products ....................................................................... 17 [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 3 of 18 pin configurations figure 1. pin diagram - 32-pin soic/32-pin pdip table 1. pin definitions - 32-pin soic/32-pin pdip pin name alt i/o type description a 0 ?a 14 input address inputs. used to select one of the 32,768 bytes of the nvsram. dq 0 -dq 7 input or output bidirectional data i/o lines . used as inp ut or output lines depending on operation. we w input write enable input, active low . wh en the chip is enabled and we is low, data on the i/o pins is written to th e specific address location. ce e input chip enable input, active low . when low , selects the chip . when high, deselects the chip. oe g input output enable, active low . the active low oe input enables the data output buffers during read cycles. deasserting oe high causes the i/o pins to tristate. v ss ground ground for the device . the device is connected to ground of the system. v cc power supply power supply inputs to the device . hsb input or output hardware store busy ( hsb ) . when low, this output indicates a hardware store is in progress. when pulled low external to the chip , it initiates a nonvolatile store operation. a weak internal pull up resistor keeps this pin high if not connected (connection optional). v cap power supply autostore capacitor . supplies power to nvsram during power loss to store data from sram to nonvolatile elements. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 4 of 18 device operation the STK14C88-3 nvsram is made up of two functional components paired in the same physical cell. these are an sram memory cell and a nonvolatile quantumtrap cell. the sram memory cell operates as a standard fast static ram. data in the sram is transferr ed to the nonvolatile cell (the store operation) or from the nonvolatile cell to sram (the recall operation). this unique architecture enables the storage and recall of all cells in parallel. during the store and recall operations, sram read and write operations are inhibited. the STK14C88-3 supports unlimited reads and writes similar to a typical sram. in addition, it provides unlimited recall operations from the nonvolatile cells and up to one million store operations. sram read the STK14C88-3 performs a read cycle whenever ce and oe are low while we and hsb are high. the address specified on pins a 0?14 determines the 32,768 data bytes accessed. when the read is initiated by an address transition, the outputs are valid after a delay of t aa (read cycle 1). if the read is initiated by ce or oe , the outputs are valid at t ace or at t doe , whichever is later (read cycle 2). the data outputs repeatedly respond to address changes within the t aa access time without the need for transitions on any control input pins, and remains valid until another address change or until ce or oe is brought high, or we or hsb is brought low. sram write a write cycle is performed whenever ce and we are low and hsb is high. the address inputs must be stable prior to entering the write cycle and must remain stable until either ce or we goes high at the end of the cycle. th e data on the common i/o pins dq 0?7 are written into the memory if it has valid t sd , before the end of a we controlled write or before the end of an ce controlled write. keep oe high during the entire write cycle to avoid data bus contention on common i/o lines. if oe is left low, internal circuitry turns off the output buffers t hzwe after we goes low. autostore operation the STK14C88-3 can be powered in one of three storage operations: during normal operation, the device draws current from v cc to charge a capacitor connected to the v cap pin. this stored charge is used by the chip to perform a single store operation. if the voltage on the v cc pin drops below v switch , the part automatically disconnects the v cap pin from v cc . a store operation is initiated with power provided by the v cap capacitor. figure 2 show s the proper connecti on of the storage capacitor (v cap ) for automatic store oper ation. a charge storage capacitor having a capacity of between 68 uf and 220 uf ( + 20%) rated at 4.7v should be provided. to reduce unnecessary nonvolatile stores, autostore and h ardware store operations are ignored, unless at least one write operation has taken place since the most recent store or recall cycle. soft ware initiated store cycles are performed regardless of whether a write operation has taken place. an optional pull-up resistor is shown connected to hsb . the hsb signal is monitored by the system to detect if an autostore cycle is in progress. if the power supply drops faster than 20 us/volt before vcc re aches v switch , then a 1 ohm resistor should be connected between v cc and the system supply to avoid momentary excess of current between v cc and v cap . autostore inhibit mode if an automatic store on power loss is not required, then v cc is tied to ground and +3.3v is applied to v cap ( figure 3 on page 5 ). this is the autostore inhibit mode, where the autostore function is disabled. if th e STK14C88-3 is operated in this configuration, references to v cc are changed to v cap throughout this data sheet. in this mode, store operations are triggered through software control. it is not permissible to change between these options ?on the fly?. figure 2. autostore mode [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 5 of 18 hardware store ( hsb ) operation the STK14C88-3 provides the hsb pin for controlling and acknowledging the store operations. the hsb pin is used to request a hardware st ore cycle. when the hsb pin is driven low, the STK14C88-3 conditionally initiates a store operation after t delay . an actual store cycle only begins if a write to the sram takes place since the last store or recall cycle. the hsb pin also acts as an open drain driver that is internally driven low to indicate a busy condition, while the store (initiated by any means) is in progress. pull up this pin with an external 10k ohm resistor to v cap if hsb is used as a driver. sram read and write operations, that are in progress when hsb is driven low by any means, are given time to complete before the store operation is initiated. after hsb goes low, the STK14C88-3 continues sram operations for t delay . during t delay , multiple sram read operatio ns take place. if a write is in progress when hsb is pulled low, it allows a time, t delay to complete. however, any sram write cycles requested after hsb goes low are inhibited until hsb returns high. the hsb pin is used to synchronize multiple STK14C88-3 while using a single larger capacitor. to operate in this mode, the hsb pin is connected together to the hsb pins from the other STK14C88-3. an external pull up resistor to v cap is required, since hsb acts as an open drain pull down. the v cap pins from the other STK14C88-3 parts are tied together and share a single capacitor. the capacitor size is scaled by the number of devices connected to it. when any one of the STK14C88-3 detects a power loss and asserts hsb , the common hsb pin causes all parts to request a store cycle. (a store takes place in those STK14C88-3 that are written sinc e the last nonvolatile cycle.) during any store operation, regardless of how it is initiated, the STK14C88-3 continues to drive the hsb pin low, releasing it only when the store is complete. after completing the store operation, the STK14C88-3 remains disabled until the hsb pin returns high. if hsb is not used, it is left unconnected. hardware recall (power up) during power up or after any low power condition (v cc < v reset ), an internal recall request is latched. when v cc once again exceeds the sense voltage of v switch , a recall cycle is automatically initiated and takes t hrecall to complete. if the STK14C88-3 is in a write state at the end of power up recall, the sram data is corrupted. to help avoid this situation, a 10 kohm resistor is connected either between we and system v cc or between ce and system v cc . software store data is transferred from the sr am to the nonvolatile memory by a software address sequence. the STK14C88-3 software store cycle is initiated by executing sequential ce controlled read cycles from six specific address locations in exact order. during the store cycle, an erase of the previous nonvolatile data is first performed followed by a program of the nonvolatile elements. when a store cycle is initiated, input and output are disabled until the cycle is completed. because a sequence of reads from specific addresses is used for st ore initiation, it is import ant that no other read or write accesses intervene in the sequence. if they intervene, the sequence is aborted and no store or recall takes place. to initiate the software store cycle, the following read se quence is performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0fc0, initiate store cycle the software sequence is clocked with ce controlled reads. when the sixth address in the sequence is entered, the store cycle commences and the chip is di sabled. it is important that read cycles and not write cycles are used in the sequence. it is not necessary that oe is low for a valid sequence. after the t store cycle time is fulfilled, the sram is again activated for read and write operation. figure 3. autostore inhibit mode [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 6 of 18 software recall data is transferred from the nonvolatile memory to the sram by a software address sequence. a software recall cycle is initiated with a sequence of read operations in a manner similar to the software store initiation. to initiate the recall cycle, the following sequence of ce controlled read operations is performed: 1. read address 0x0e38, valid read 2. read address 0x31c7, valid read 3. read address 0x03e0, valid read 4. read address 0x3c1f, valid read 5. read address 0x303f, valid read 6. read address 0x0c63, initiate recall cycle internally, recall is a two step procedure. first, the sram d ata is cleared, and then the nonvolatile information is trans - ferred into the sram cells. after the t recall cycle time, the sram is once again ready for read and write operations. the recall operation does not alter the data in the nonvol - atile elements. the nonvolatile data can be recalled an u nlimited number of times. preventing store the store function can be disabled on the fly by holding hsb high with a driver capable of sourcing 30 ma at a v oh of at least 2.2v, because it has to overpower the internal pull down device. this device drives hsb low for 20 s at the onset of a store. when the STK14C88-3 is connected for autostore operation (system v cc connected to v cc and a 68 f capacitor on v cap ) and v cc crosses v switch on the way down, the STK14C88-3 attempts to pull hsb low. if hsb does not actually get below v il , the part stops trying to pull hsb low and aborts the store attempt. hardware protect the STK14C88-3 offers hardware protection against inadvertent store operation and sram writes during low voltage conditions. when v cap STK14C88-3 is a high speed memory. it must have a high frequency bypass capacitor of approximately 0.1 f connected between v cc and v ss, using leads and traces that are as short as possible. as with all high speed cmos ics, careful routing of power, ground, and signals reduce circuit noise. low average active power cmos technology provides th e STK14C88-3 the benefit of drawing significantly less current when it is cycled at times longer than 50 ns. figure 4 and figure 5 show the relationship between i cc and read or write cycle time. worst case current consumption is shown for both cmos and ttl input levels (commercial temperat ure range, vcc = 3.6v, 100% duty cycle on chip enable). only standby current is drawn when the chip is disabled. the overall average current drawn by the STK14C88-3 depends on the following items: 1. the duty cycle of chip enable 2. the overall cycle rate for accesses 3. the ratio of reads to writes 4. cmos versus ttl input levels 5. the operating temperature 6. the v cc level 7. i/o loading figure 4. current ve rsu s cycle time (read) figure 5. current vers u s cycle time (write) [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 7 of 18 best practices nvsram products have been used effectively for over 15 years. while ease-of-use is one of t he product?s main system values, experience gained working with hundreds of applications has resulted in the following suggestions as best practices: the nonvolatile cells in an nvsram are programmed on the test floor during final test and quality assurance. incoming inspection routines at customer or contract manufacturer?s sites, sometimes, reprogram t hese values. final nv patterns are typically repeating patterns of aa, 55, 00, ff, a5, or 5a. end product?s firmware should not assume an nv array is in a set programmed state. routines that check memory content values to determine first time system configuration and cold or warm boot status, should always program a unique nv pattern (for example, a complex 4-byte pattern of 46 e6 49 53 hex or more random bytes) as part of the final system manufacturing test to ensure these system rout ines work consistently. power up boot firmware routines should rewrite the nvsram into the desired state. while the nvsram is shipped in a preset state, best practice is to again rewrite the nvsram into the desired state as a safeguard against events that might flip the bit inadvertently (program bugs or incoming inspection routines). the v cap value specified in this data sheet includes a minimum and a maximum value size. best practice is to meet this requirement and not exceed the max v cap value because the higher inrush currents may reduce the reliability of the internal pass transistor. customers who want to use a larger v cap value to ensure there is extra st ore charge should discuss their v cap size selection with cypress to understand any impact on the v cap voltage level at the end of a t recall period. table 2. hardware mode selection ce we hsb a 13 ? a 0 mode i/o power h x h x not selected output high z standby l h h x read sram output data active [1] l l h x write sram input data active x x l x nonvolatile store output high z i cc2 [2] l h h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0fc0 read sram read sram read sram read sram read sram nonvolatile store output data output data output data output data output data output data active [1, 3, 4, 5] l h h 0x0e38 0x31c7 0x03e0 0x3c1f 0x303f 0x0c63 read sram read sram read sram read sram read sram nonvolatile recall output data output data output data output data output data output data active [1, 3, 4, 5] notes 1. i/o state assumes oe < v il . activation of nonvolatile cycles does not depend on state of oe . 2. hsb store operation occurs only if an sram write has been done sinc e the last nonvolatile cycle. af ter the store (if any) complete s, the part will go into standby mode, inhibiting all operations until hsb rises. 3. ce and oe low and we high for output behavior. 4. the six consecutive addresses must be in the order listed. we must be high during all six consecutive ce controlled cycles to enable a nonvolatile cycle. 5. while there are 15 addresses on the STK14C88-3, only the lower 14 are used to control software modes. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 8 of 18 maximum ratings exceeding maximum ratings may s horten the useful life of the device. these user guidelines are not tested. storage temperature ................................. ?65 c to +150 c temperature under bias.............................. ?55 c to +125 c supply voltage on v cc relative to gnd ..........?0.5v to 7.0v voltage on input relative to vss............ ?0.6v to v cc + 0.5v voltage on dq 0-7 or hsb ....................... ?0.5v to vcc + 0.5v power dissipation ................... ... ................................... 1.0w dc output current (1 output at a time, 1s duration) .... 15 ma operating range range ambient temperature v cc commercial 0 c to +70 c 3.0v to 3.6v industrial -40 c to + 85 c 3.0v to 3.6v dc electrical characteristics over the operating range (v cc = 3.0v to 3.6v) [6] parameter description test conditions min max unit i cc1 average v cc current t rc = 35 ns t rc = 45 ns dependent on output loadin g and cycle rate. v alues obtained without output loads. i out = 0 ma. commercial 50 42 ma ma industrial 52 44 ma ma i cc2 average v cc current during store all inputs do not care, v cc = max average current for duration t store 3 ma i cc3 average v cc current at t rc = 200 ns, 5v, 25c typical we > (v cc ? 0.2v). all other inputs cycling. dependent on output loading and cycle rate. values obtained without output loads. 9 ma i cc4 average v cap current during autostore cycle all inputs do not care, v cc = max average current for duration t store 2 ma i sb1 [7] average v cc current (standby, cycling ttl input levels) t rc =35ns, ce > v ih t rc =45ns, ce > v ih commercial 18 16 ma industrial 19 17 ma i sb2 [7] v cc standby current (standby, stable cm os input levels) ce > (v cc ? 0.2v). all others v in < 0.2v or > (v cc ? 0.2v). 1 ma i ix input leakage current v cc = max, v ss < v in < v cc -1 +1 a i oz off state output leakage current v cc = max, v ss < v in < v cc , ce or oe > v ih or we < v il -1 +1 a v ih input high voltage 2.2 v cc + 0.5 v v il input low voltage v ss ? 0.5 0.8 v v oh output high voltage i out = ?4 ma except hsb 2.4 v v ol output low voltage i out = 8 ma except hsb 0.4 v v bl logic ?0? voltage on hsb output i out = 3 ma 0.4 v v cap storage capacitor between v cap pin and vss, 68 to 220uf + 20%, 4.7v rated. 54 264 uf notes 6. v cc reference levels throughout this data sheet refer to v cc if that is where the power s upply connection is made, or v cap if v cc is connected to ground. 7. ce > v ih will not produce standby current levels until any nonvolatile cycle in progress has timed out. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 9 of 18 data retention and endurance parameter description min unit data r data retention 100 years nv c nonvolatile store operations 1,000 k capacitance in the following table, the capacitance parameters are listed. [8] parameter description test conditions max unit c in input capacitance t a = 25 c, f = 1 mhz, v cc = 0 to 3.0 v 5 pf c out output capacitance 7 pf thermal resistance in the following table, the thermal resistance parameters are listed. [8] parameter description test conditions 32-soic 32-pdip unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and p rocedures for measuring thermal impedance, per eia / jesd51. tbd tbd c/ w jc thermal resistance (junction to case) tbd tbd c/ w figure 6. ac test loads ac test conditions 3.3v output 30 pf r1 317 r2 351 input pulse levels .................................................. 0 v to 3 v input rise and fall times (10% - 90%)........................ < 5 ns input and output timing referenc e levels ......... .......... 1.5 v note 8. these parameters are guaranteed by design and are not tested. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 10 of 18 ac switching characteristics sram read cycle parameter description 35 ns 45 ns unit min max min max cypress parameter alt t ace t elqv chip enable access time 35 45 ns t rc [9] t avav, t eleh read cycle time 35 45 ns t aa [10] t avqv address access time 35 45 ns t doe t glqv output enable to data valid 15 20 ns t oha [10] t axqx output hold after address change 5 5 ns t lzce [11] t elqx chip enable to output active 5 5 ns t hzce [11] t ehqz chip disable to output inactive 13 15 ns t lzoe [11] t glqx output enable to output active 0 0 ns t hzoe [11] t ghqz output disable to output inactive 13 15 ns t pu [8] t elicch chip enable to power active 0 0 ns t pd [8] t ehiccl chip disable to power standby 35 45 ns switching waveforms figure 7. sram read cycle 1: address controlled [9, 10] figure 8. sram read cycle 2: ce and oe controlled [9] w 5& w $$ w 2+$ $''5(66 '4'$7$287 '$7$9$/,' $''5(66 w 5& &( w $&( w /=&( w 3' w +=&( 2( w '2( w /=2( w +=2( '$7$9$/,' $&7,9( 67$1'%< w 38 '4'$7$287 ,&& notes 9. we and hsb must be high during sram read cycles. 10. i/o state assumes ce and oe < v il and we > v ih ; device is continuously selected. 11. measured 200 mv from steady state output voltage. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 11 of 18 table 3. sram write cycle parameter description 35 ns 45 ns unit min max min max cypress parameter alt t wc t avav write cycle time 35 45 ns t pwe t wlwh, t wleh write pulse width 25 30 ns t sce t elwh, t eleh chip enable to end of write 25 30 ns t sd t dvwh, t dveh data setup to end of write 12 15 ns t hd t whdx, t ehdx data hold after end of write 0 0 ns t aw t avwh, t aveh address setup to end of write 25 30 ns t sa t avwl, t avel address setup to start of write 0 0 ns t ha t whax, t ehax address hold after end of write 0 0 ns t hzwe [11,12] t wlqz write enable to output disable 13 15 ns t lzwe [11] t whqx output active after end of write 5 5 ns switching waveforms figure 9. sram write cycle 1: we controlled [13, 14] figure 10. sram write cycle 2: ce controlled [13, 14] t wc t sce t ha t aw t sa t pwe t sd t hd t hzwe t lzwe address ce we data in data out data valid high impedance previous data t wc address t sa t sce t ha t aw t pwe t sd t hd ce we data in data out high impedance data valid notes 12. if we is low when ce goes low, the outputs remain in the high impedance state. 13. ce or we must be greater than v ih during address transitions. 14. hsb must be high during sram write cycles. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 12 of 18 autostore or power up recall parameter alt description STK14C88-3 unit min max t hrecall [15] t restore power up recall duration 550 s t store [16, 17] t hlhz store cycle duration 10 ms t vsbl [16] low voltage trigger (v switch ) to hsb low 300 ns v reset low voltage reset level 2.4 v v switch low voltage trigger level 2.7 2.95 v t delay [16] t blqz time allowed to complete sram cycle 1 s switching waveforms figure 11. autostore/power up recall we notes 15. t hrecall starts from the time v cc rises above v switch . 16. ce and oe low and we high for output behavior. 17. hsb is asserted low for 1us when v cap drops through v switch . if an sram write has not taken place since the last nonvolatile cycle, hsb will be released and no store will take place. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 13 of 18 software controlled store/recall cycle the software controlled store/recall cycle follows. [18, 19] parameter alt description 35 ns 45 ns unit min max min max t rc [16] t avav store/recall initiation cycle time 35 45 ns t sa [18, 19] t avel address setup time 0 0 ns t cw [18, 19] t eleh clock pulse width 25 30 ns t hace [18, 19] t elax address hold time 20 20 ns t recall recall duration 20 20 s switching waveforms figure 12. ce controlled software store/recall cycle [19] t rc t rc t sa t sce t hace t store / t recall data valid data valid 6#sserdda 1#sserdda high impedance address ce oe dq (data) notes 18. the software sequence is clocked on the falling edge of ce without involving oe (double clocking will abort the sequence). 19. the six consecutive addr esses must be read in the order listed in the mode selection table. we must be high during all six consecutive cycles. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 14 of 18 hardware store cycle parameter alt description STK14C88-3 unit min max t phsb t hlhx hardware store pulse width 15 ns t dhsb [16, 20] t recover, t hhqx hardware store high to inhibit off 700 ns t hlbl hardware store low to store busy 300 ns switching waveforms figure 13. hardware store cycle 3+6% note 20. t dhsb is only applicable after t store is complete. [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 15 of 18 ordering information these parts are not recommended for new designs. speed (ns) ordering code package diagram package type operating range 35 STK14C88-3nf35tr 51-85127 32-pin soic commercial STK14C88-3nf35 51-85127 32-pin soic STK14C88-3nf35itr 51-85127 32-pin soic industrial STK14C88-3nf35i 51-85127 32-pin soic 45 STK14C88-3nf45tr 51-85127 32-pin soic commercial STK14C88-3nf45 51-85127 32-pin soic STK14C88-3nf45itr 51-85127 32-pin soic industrial STK14C88-3nf45i 51-85127 32-pin soic all parts are pb-free. the above table contains final information . please contact your local cypress sales representative for a vailability of these parts packaging option: tr = tape and reel blank = tube speed: 35 - 35 ns 45 - 45 ns package: n = plastic 32-pin 300 mil soic part numbering nomenclature stk14c88- 3n f 45 i tr temperature range: blank - commercial (0 to 70c) w = plastic 32-pin 600 mil dip lead finish f = 100% sn (matte tin) i - industrial (-40 to 85c) [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 16 of 18 package diagrams figure 14. 32-pin (300 mil) soic (51-85127) pin 1 id seating plane 1 16 17 32 dimensions in inches[mm] min. max. 0.292[7.416] 0.299[7.594] 0.405[10.287] 0.419[10.642] 0.050[1.270] typ. 0.090[2.286] 0.100[2.540] 0.004[0.101] 0.0100[0.254] 0.006[0.152] 0.012[0.304] 0.021[0.533] 0.041[1.041] 0.026[0.660] 0.032[0.812] 0.004[0.101] reference jedec mo-119 part # s32.3 standard pkg. sz32.3 lead free pkg. 0.014[0.355] 0.020[0.508] 0.810[20.574] 0.822[20.878] 51-85127 *b [+] feedback [+] feedback not recommended for new designs
STK14C88-3 document number: 001-50592 rev. *d page 17 of 18 document history page document title: STK14C88-3 256 kbit (32k x 8) autostore nvsram document number: 001-50592 rev. ecn no. orig. of change submission date description of change ** 2625096 gvch/pyrs 12/19/2008 new data sheet *a 2821358 gvch 12/04/2009 added a note in ordering information mentioning that these parts are n ot recommended for new designs. added ?not recommended for new designs? watermark in the pdf. added contents on page 2.. *b 2902527 gvch 04/05/2010 removed inactive parts from ordering information table. *c 3054310 gvch/keer 10/11/2010 removed inactive parts (STK14C88-3wf35, STK14C88-3wf35i) from orderi ng information table and the package diagram. *d 3165737 gvch 02/08/2011 added ?not recommended for new designs? watermark in the pdf. [+] feedback [+] feedback not recommended for new designs
document number: 001-50592 rev. *d revised february 11, 2011 page 18 of 18 all products and company names mentioned in this document may be the trademarks of their respective holders. STK14C88-3 ? cypress semiconductor corporation, 2008-2011. the information contained herein is subject to change without notice. cypress s emiconductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or other rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement wi th cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. any source code (software and/or firmware) is owned by cypress semiconductor corporation (cypress) and is protected by and subj ect to worldwide patent protection (united states and foreign), united states copyright laws and internatio nal treaty provisions. cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of, and compile the cypress source code and derivative works for the sole purpose of creating custom software and or firmware in su pport of licensee product to be used only in conjunction with a cypress integrated circuit as specified in the applicable agreement. any reproduction, modification, translation, compilation, or repre sentation of this source code except as specified above is prohibited without the express written permission of cypress. disclaimer: cypress makes no warranty of any kind, express or implied, with regard to this material, including, but not limited to, the implied warranties of merchantability and fitness for a particular purpose. cypress reserves the right to make changes without further notice to t he materials described herein. cypress does not assume any liability arising out of the application or use of any product or circuit described herein. cypress does not authori ze its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. the inclusion of cypress? prod uct in a life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies cypress against all charges. use may be limited by and subject to the applicable cypress software license agreement. sales, solutions and legal information worldwide sales and design support cypress maintains a worldwide network of offices, solution centers, manufacturer?s representative s, and distributors. to find t he office closest to you, visit us at cypress.com/sales. products automotive cypress.co m/go/automotive clocks & buffers cypress.com/go/clocks interface cypress. com/g o/interface lighting & power control cypress.com/go/powerpsoc cypress.com/ go/plc memory cypress.com/go/memory optical & image sensing cypress.com/go/ image psoc cypress.com/go/psoc touch sensing cypress.com/go/ touch usb controllers cypress.com/go/ usb wireless/rf cypress.com/go/wireless psoc solutions psoc.cypress.com/solutions psoc 1 | psoc 3 | psoc 5 [+] feedback [+] feedback not recommended for new designs

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